An important trend in the development of the integrated circuitry technology is scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) to improve integration level and reduce manufacturing cost. However, the performance of semiconductor materials (e.g., carrier mobility) and the performance of the MOSFETs (e.g., threshold voltage) may also deteriorate as the size of the MOSFETs decreases.
A MOSFET may have increased carrier mobility due to appropriate stress being applied to a channel region thereof, resulting in a reduced ON resistance and an enhanced switching speed of the device. When the device is an n-type MOSFET, tensile stress may be applied to the channel region along a longitudinal direction thereof and compressive stress may be applied to the channel region along a lateral direction thereof, so as to improve the mobility of electrons as the carriers. On the other hand, when the transistor is a p-type MOSFET, compressive stress may be applied to the channel region along the longitudinal direction thereof and tensile stress may be applied to the channel region along the lateral direction thereof, so as to improve the mobility of holes as the carriers.
Desirable stress can be generated by forming a source region and a drain region using a semiconductor material different from that of a semiconductor substrate. For the n-type MOSFET, Si:C source and drain regions formed on a Si substrate may function as a stressor which applies the tensile stress to the channel region along the longitudinal direction thereof. For the p-type MOSFET, SiGe source and drain regions formed on a Si substrate may function as a stressor which applies the compressive stress to the channel region along the longitudinal direction thereof.
FIGS. 1-4 are schematic views showing semiconductor structures formed in various stages in a flow for manufacturing a MOSFET with enhanced stress according to a method of the prior art, in which FIGS. 1a, 2a, 3a and 4a show cross-section views of the respective semiconductor structures along a longitudinal direction of a channel region, FIGS. 3b and 4b show cross-section views of the respective semiconductor structures along a lateral direction of the channel region, and FIGS. 1b, 2b, 3c and 4c show top views of the respective semiconductor structures. In these figures, line AA represents a position where the cross-section views are taken along the longitudinal direction of the channel region, and line BB represents a position where the cross-section views are taken along the lateral direction of the channel region.
This method begins with the semiconductor structure shown in FIGS. 1a and 1b, in which a shallow trench isolation 102 is formed in a semiconductor substrate 101 to define an active region for the MOSFET. A gate stack surrounded by a spacer 105 is formed on the semiconductor substrate 101. The gate stack comprises a gate dielectric 103 and a gate conductor 104.
By using the shallow trench isolation 102, the gate conductor 104 and the spacer 105 as a hard mask, the semiconductor substrate 101 is etched to a desired depth so as to form openings in the semiconductor substrate at positions corresponding to a source region and a drain region, respectively, as shown in FIGS. 2a and 2b. 
A semiconductor layer 106 is grown epitaxially on an exposed surface of the semiconductor substrate 101 within each of the openings so as to form the source region and the drain region. A portion of the semiconductor substrate 101 which is beneath the gate dielectric 103 and between the source region and the drain region functions as a channel region.
The semiconductor layer 106 is grown selectively from the surface of the semiconductor substrate 101. That is, the semiconductor layer 106 is grown at different growth rates on different crystalline surfaces of the semiconductor substrate 101. In an example in which the semiconductor substrate 101 comprises Si and the semiconductor layer 106 comprises SiGe with a Ge atomic percentage of about 10-15%, the semiconductor layer 106 has a slowest growth rate on a crystallographic surface {1 1 1} of the semiconductor substrate 101. As a result, the formed semiconductor layer 106 comprises not only a main plane (100) parallel to the surface of the semiconductor substrate 101, but also facets {1 1 1} at positions adjoining the shallow trench isolation 102 and the spacer 105, which is called an edge effect of the growth of the semiconductor layer 106, as shown in FIGS. 3a, 3b and 3c. 
However, the small facets of the semiconductor layer 106 are not desirable because they cause more free surfaces, which release stress from the semiconductor layer 106, thereby reducing the stress applied to the channel region.
Next, the surface of the semiconductor layer 106 is silicidated to form a metal silicide layer 107, as shown in FIGS. 4a, 4b and 4c. The silicidation consumes a part of the semiconductor layer 106. Due to the existence of the small facets of the semiconductor layer 106, the silicidation may occur along the small facets and finally may even reach the semiconductor substrate 101.
However, the silicidation in the semiconductor substrate 101 is undesirable because it may form the metal silicide in a junction region, which leads to increased junction leakage.
Thus, it is desirable to suppress the edge effect in the semiconductor layer of the source and drain regions in the MOSFET with enhanced stress.